These are the key questions you should consider when you prepare specifications for bare–board test:

Various industry groups have established standards to effectively define common electrical test requirements and data formats. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) offers a selection of documents. ANSI–IPC–D–350 and in particular, IPC–D–356 are useful definitions of data formats for electrical test purposes. IPC–ET–652 is an excellent overview of many electrical test requirements and fixture considerations, including further technical details on the major topics discussed in this paper. For military applications, MIL–55110 Revision D provides definitive electrical test parameters.

Do you specify PCB electrical test?
Most specifiers of bare PCBs are technically sophisticated, but they would readily admit that their expertise is focused on design of electronics or software, rather than the process–related details of PCB fabrication and test. They often assume that boards will be tested, but make no explicit statement of this expectation when making purchase commitments. In other cases, electrical test is explicitly required, but test conditions are unspecified. Vague statements such as "100% electrical test required," or, "shorts and opens tests required," are subject to excessive interpretation.

Keep in mind that a board manufacturer who bids for this business must spend hundreds to thousands of dollars to fabricate a test fixture and prepare a test program. He has a variety of options for varying costs and effectiveness. Some of his customers may actually prefer a very cheap test, with limited fault coverage, or no test whatsoever. If you expect the manufacturer to make a significant investment in tooling and data preparation, it stands to reason that you must carefully state your requirements. If you expect electrical test, say so. Refer explicitly to applicable standards or test conditions unique to your product.

What should be tested?
Electrical test of most circuit boards requires preparation of a test fixture that is unique to each specific board design. The fixture interfaces the test system to a field of testpoints arranged to probe the features of interest on a specific product. Various types of fixtures can be used, depending upon the product, and the type of test system employed. The cost of preparing this test fixture is ultimately passed on to the specifier. The total number of points contacted, requirements for simultaneous dual–side probing, and the pitch (spacing) of the test points, each affects fixture cost. Very closely spaced targets of small size require the use of more expensive probing techniques. The fixture design process includes decisions as to which PCB features should have assigned testpoints. These decisions can affect whether the PCB actually receives a valid 100% test.

Most board manufacturers and test services will take reasonable steps to minimize fixture cost. For example, if three possible test points occur along the length of a copper trace which has no branches, then the center contact is redundant, and need not be probed. Simply placing a probe at each end of the trace is generally sufficient to ensure continuity of the trace. This example illustrates the rule: probes need to be placed only at the endpoints of traces or trace branches. Optimizing test probe assignments is an important means of controlling test fixture expense,especially for hand-wired test fixtures. Optimization is of less value with modern 'tilt pin' figures where the cost per testpoint is greatly reduced. With this latter fixture type, the hazards of excessive optimization can be avoided by requiring the supplier to test all probe-able points.

Figure 1 illustrates the basic rule of testpoint optimization for bare–board fixtures.

Figure 1

In this example, probes should be placed at locations A, C, and D. A probe is not required at location B because the continuity of the network from A to C already establishes continuity to point B. The example above will be extended as we consider the board in three dimensions.

Probe placement rules should be clearly understood. It is not uncommon to observe a test fixture that has been over optimized (desirable testpoints have been omitted). This can result from human error in manual editing methods, or from data and software problems in automatic editing. Testpoints are sometimes deleted because they are at locations that are difficult or expensive to probe.

For many customers an initial exposure to fixture and testpoint optimization issues occur during development of test fixtures for fully assembled boards. Most of the fixtures required only a single testpoint per network. However, the testpoint selections are somewhat different for bare–board test. Designers of bareboard test fixtures will sometimes err in removing an excessive number of ground or power points from the fixture of a multilayer board.

Consider the board as a three dimensional circuit. Any component mounting location tied to an internal power or ground plane or internal signal layer, is the end of a short vertical branch in that network. According to the optimization rule, described above, these points must be probed. By comparison, loaded board fixtures usually pick up a smaller number of power and ground points because the failure of a part to be properly powered will exhibit symptoms affecting other pins during attempted operation of the circuit.

Another probe selection issue is the assignment of testpoints to any single–point networks on the board. These plated pads, or holes, are not intended to connect to any other feature.

Single–point networks occur at mounting points for hardware, etc. In some cases, it does no harm if a single–point network is shorted to a nearby circuit feature or inner layer. But in other cases, it does matter. Don't assume that the fixture used to test your board will probe these points. To guarantee full test coverage, explicitly require test of single–point networks.

Boards with surface–mount components or card–edge fingers on both surfaces require simultaneous dual–side probing to provide 100% fault coverage. In such cases, there are traces ending on each side of the board, and these trace ends must be probed simultaneously to assure trace continuity from side to side. To avoid the expense of a dual–side fixture, a technique called "flip testing" is sometimes used. A fixture is built to permit the board to be tested one side at a time, flipping the PCB over, between sides. Less than 100% fault coverage is achieved however, because the test fails to detect open feedthroughs between the two sides. Since separate probe patterns are still required for each side of the board, the fixture cost savings are minimal. Generally, you should avoid flip testing, if you expect 100% fault coverage. Modern test systems and fixtures permit simultaneous dual-side test.

To summarize:
For 100% coverage you should require that testpoints be located at the endpoints of all traces or trace branches, at all component holes 'fed' by internal layer connections, at all surface component mounting pads which end traces (or associated test pads), and at all single–point networks (isolated points).

For boards containing surface–mount pads and/or card–edge fingers that terminate traces on both sides of the board, you should explicitly require simultaneous dual–side access fixturing to verify continuity between sides.

Why test parameters should be specified.
Basic electrical test ultimately involves electrical measurements to be made on the individual product. Expected connections and expected isolations are verified. Specific requirements are essential to define what constitutes a valid continuity or isolation, and the stimulus conditions under which that judgment is made.

Useful electrical test standards have been developed by several organizations. A simple reference to IPC–ET–652 or MIL–55110D is often adequate from a technical perspective. While these standards address the needs of most commercial and military applications, the specifier who does not take the time to understand them may be in for some surprises after the boards are fully assembled.

The classic and most frequent electrical defects observed on bare circuit boards are simple shorts and opens. These are typically easy to detect. But sensitive circuits in the final product can be made non–functional by more subtle (and admittedly less common) types of errors.

For example, a very small amount of moisture (or other contamination) trapped within the board may conduct sufficient leakage current to cause serious problems for an operational amplifier input. Yet this type of bare–board failure will NOT be detected by many older types of bare–board electrical test equipment. Even modern equipment may miss such failures when programmed with test thresholds geared to maximize throughput, at the expense of measurement accuracy. Worse yet, the leakage currents carried by contaminants on (or within) a board can vary significantly with fluctuations in temperature and humidity. The use of modern, sensitive test systems, and more aggressive test specifications, will increase the likelihood of detecting even small amounts of such contaminants during bare–board test. This, in turn, reduces the likelihood of field failures resulting from such contamination.

Electrical test parameters usually include the following:

Continuity Threshold
The first phase of a bare–board test is the continuity test. This test should verify that each circuit trace is intact. Expected connections which exhibit resistance in excess of the value set for the continuity resistance test Pass/Fail threshold will FAIL the test, and should be reported as OPEN. Early generations of test equipment had little or no adjustment range, and this threshold might be set no lower than a few hundred ohms. Obviously a circuit trace would have to be wide open to fail such a test. Modern equipment and fixtures readily permit the continuity test threshold to be set to a few ohms. This is sufficiently low to detect more subtle errors. Most of the modern test standards require circuit board continuities to be verified at 5 to 10 ohms, or less. This level of performance is economically practical for general purpose test, so long as the test facility uses modern equipment and good clean fixtures.

IPC–ET–652 suggests a continuity threshold of 50 ohms, 20 ohms, or less, depending on whether the product is classified as "general electronic–Class 1,' "dedicated service–Class 2", or "high reliabilityClass 3." Mil–55110D generally requires the threshold be set at 10 ohms or less. Setting the continuity threshold excessively low increases the demands placed on the test fixture, and may slow the test process due to the need to re–test false open reports caused by contact resistance problems within the test fixture.

Continuity Test Current
Some early test systems delivered large electrical currents to the product during continuity test. This was not a problem for older PCBs that had relatively large conductor sizes. Since the conductors on modern circuit boards are considerably finer, consider the maximum test current that can be delivered to the board, without risk of damage. A few systems with stimulus levels of up to one ampere are still in use. Therefore, specify a maximum amount of current that may be passed through the board during continuity test, without limiting the value excessively. This will permit use of the widest range of test systems, while protecting the product from damage. A minimum level need not be specified, since the use of adequate test current is implied by your stated requirement for continuity test threshold resistance.
Modern solid–state test systems are quite sensitive. They can make accurate continuity measurements, while delivering no more than 10 to 50 milliamperes to the product.

Isolation Threshold
The second phase of a bare–board test is the isolation test. This test should verify that each network is well isolated from the rest of the board. The test system will ground all networks except the network under test. The test system will then measure the resistance between the network under test and the ground representing all other networks. The system detects the parallel combination of all leakage resistance, from the tested network to the balance of the board.

If the measured resistance is less than the isolation test resistance Pass/Fail threshold, the tested network will FAIL. Some test systems will differentiate the failures as either LEAKS or SHORTS, depending on how low the failing resistance value is. One might imagine this measurement as being made with an ohmmeter offering one red wire, and several thousand black wires.

Older test systems did not permit the operator to set the isolation test threshold any higher then ten thousand ohms or so. Modern test systems should permit settings as high as 100 to 1000 Megohms for this test, depending on the applied voltage. IPC–ET–652 suggests an isolation threshold of 500K ohms, or greater than 2 Megohms, depending on whether the product is classified as "general electronic–Class l", "dedicated service–Class 2", or "high reliability–Class 3" Mil55110D generally requires the threshold be set at 2 Megohms or more.

You should select a threshold that meets the performance requirements of your product. Two Megohms is probably not adequate for many types of analog circuits. Good test systems show little degradation of speed or other attributes at 10 Megohms, and some are available with good performance at 100 Megohms or more.

Isolation Voltage
During the isolation test of each network, a small amount of current is injected into the network. If the network is well isolated, it is elevated in voltage by this current. The network will act as a capacitor, and the arriving current will steadily charge it to higher voltage levels. In this case the voltage of the network under test will ramp up to a value determined by a voltage limiting circuit in the test system. On the other hand, if the network leaks significant current to other networks, then the test current may be unable to charge it up to the voltage limit. This is the case when the isolation test fails.

Higher voltages are useful in assuring accuracy for the higher isolation test resistance Pass/Fail thresholds. A given leakage resistance will leak more current with a higher applied voltage, and is more easily detected. High voltage can also encourage the breakdown of ionic contaminants, increasing the leakage current flow and helping to ensure their detection during test. These are the primary reasons for specifying the open–circuit test voltage during the isolation test of the product. Of course, the voltage should not be so high that there is any risk of damaging the product.

Older solid–state test systems usually operate with a fixed isolation test voltage in the 5–10 volt range. This limits their Isolation Resistance Threshold range. Modern solid–state systems offer up to 250 volt capability, with the exact value fully programmable. Relay type systems offer higher voltage, but are slow, expensive, and most often used for military cable and harness test purposes.

IPC-ET-652 recommends only the use of voltage "..high enough to provide sufficient current resolution for the measurement", Mil-55110D requires the application of at least 40 volts (or twice the voltage rating of the board, whichever is greater) during isolation test by automatic equipment. Generally, use at least 100 volts when isolation test over 10 Megohms is specified. This ensures adequate throughput and resolution.

Isolation Test Method
There are interesting differences among the algorithms by which various test systems attempt to detect isolation failures on the product. Each method is generally for detection of hard shorts and/or highly–localized leakage, but they vary in their ability to detect distributed contaminants.

For example, the isolation test performed by "flying–probe" test systems is fundamentally different from the test of high–performance bare–board test systems. Flyingprobe test systems are unable to contact all networks simultaneously, so they can't measure the total leakage from a given network to the entire balance of the board in a single measurement. They are limited to measuring the insulation resistance between specific network pairs. Using the ohmeter analogy given earlier, you might think of the flyingprobe test system as having one black and one red lead, while a general purpose bare board tester looks like an ohmeter with one red lead and thousands of black leads, each of which is switchable among the product test points.

If the measurement system in the flying–probe system were perfect, one could measure the individual leakages from the network under test to all other nets individually using a flying–probe system, and then total individual leakages. But in the real world, there is too much measurement system error added to each of the thousands of tiny individual leakage measurements, hence this technique does not work (the desired data are lost among the accumulated measurement errors). As a result, flying–probe systems can detect hard shorts and concentrated isolation resistance failures, but they are less sensitive to distributed contamination type defects. In view of this limit then, for speed reasons, they are often restricted to measurement of nets physically adjacent to the network in question. If you're concerned with high–impedance/high–voltage isolation test results, you should consider the limitations of this type test system.

In any event, flying–probe systems are rather slow, requiring ten minutes to hours to test each product. They are typically limited to very small production runs where the cost of a test fixture is considered prohibitive. They remain very useful in that application.

Some general–purpose bare–board test systems share a related problem regarding the isolation test algorithm. In an attempt to minimize the number of switching operations required per product, these systems test groups of networks against other groups, resulting in a reduction in the total number of isolation measurements required. (For a board with 'n' networks, the number of measurements required is reduced to approximately the log of 'n', base 2). In this case, the problem is the risk of missing a distributed leakage from one network to several others. If you're concerned about this, you should verify that the test system used to test your boards performs one isolation measurement for every isolated network or single–point network on the product. If the board has 1000 networks, for example, 1000 isolation measurements should be made–one of each network– while all other networks are grounded.

Embedded Resistor Tests
Some board manufacturers offer the capability to embed passive components, such as resistors, within the printed circuit substrate. Modern bare–board test systems can be equipped with options to permit testing of these resistors. Carefully analyze the energy–limiting protection mechanisms used within these test systems. It would not be desirable to accidentally place destructive voltage across all of these passive components at the final test stage of production.

Characteristic Impedance (Z_o) Test
Bare PCBs intended for very high speed digital circuit, or RF/microwave applications, require careful control of the characteristic impedance (or RF impedance) of traces on the board. The industry frequently refers to such boards as "controlled–impedance" boards. Factors that affect RF impedance include the relative dielectric constant of the laminate materials, copper thickness, trace width, distance from the ground plane and other features, plus several others.

Bare–board fixtures and test systems do not generally offer the RF capability required to evaluate characteristic impedance (ZO). A limited number of special testpoints in the fixture can be connected to external equipment for this purpose. However, for a variety of reasons, including cost, this test is usually conducted on a sample basis, using independent fixturing or manual probing of the product. A Time Domain Reflectometer or Network Analyzer would typically be used for this purpose. A variety of instruments of this type is available.

Where does electrical test program data originate?
Before electrical test of a bare–board can occur, two major preparations must be made. First, a suitable test fixture must be constructed to interface the appropriate product test locations to specific test points of the test system. Second, the test system must be loaded with a test program that specifies the manner in which these test points should be observed to be interconnected by a properly fabricated product. Significant data processing considerations apply to these preparations.
Fixture and test program data can be generated by the following methods:

Self–learn Method
This was the test program generation method provided with the earliest automatic bare–board test systems. It's still the most popular method, although its use is now in decline. It remains as a useful fallback method in virtually all board shops.

A test fixture is required to initiate self–learn program generation, and it can be produced by several methods.

Originally, most PCBs were of the through–hole variety. Since a drilled hole existed at virtually all points of interest, the fixture probe placement data was derived from the product drill tape. Singleside access was usually adequate. Many fixtures for through–hole boards are still built this way.

The next evolution occurred as SMT products appeared, with target locations that lacked any drilled hole. At first, these features were manually digitized, and appended to the drill–tape file used to drill the test fixture. This remains a common method of fixturing SMT products, especially those with mixed SMT and through–hole technology.

Next came the arrival of Gerber file processing software. Using this software, the Gerber photoplot image of the product is analyzed, and the computer assigns testpoint locations for both through–hole and SMT sites. This process remains in use today and, as will be described later, it was eventually extended to include automatic creation of a test program.

To self–learn the test program, the fixture is assembled according to a data set derived as described above, and installed on the test system. A sample product is placed on the fixture, and the system is instructed to "learn" the interconnects. This test program is then stored and used to evaluate the remaining products. If most other boards pass, then the original sample is presumed to be OK If many other boards fail with an identical defect report, then one suspects that the original sample was defective. In that case, a new program is created from the largest identical group of boards.

There are several problems with the self–learn method. Mechanical errors in the fixture that cause unstable test results can confuse evaluation of the quality of the test program generated by the learning process. For example, if certain probes are slightly mix–located in the fixture, they will make intermittent contact to the product. As connections come and go on subsequent learn and/or test attempts, considerable time is lost tracking down the cause of these irregularities. Is the open or short occuring because of a fixture problem or a product problem? Repeated cycles of self–learn and evaluation become likely as product and fixture complexity increases.

A highly–skilled operator is required to correctly evaluate self–learn results and develop a meaningful program by differentiating product errors from programming errors.

The fixture fabrication process is subject to errors in probe allocation and placement. A few extra probes do little harm. But probes inadvertently optimized out of the fixture result in untested portions of the product. A self–learned program can never consider the related product features because the test system is not connected to them. In other words, if a probe is left completely out of a fixture (or if the wire to that probe is broken internally), then the test system will quite happily learn that test point as being connected to nothing else, like other single points, and will always pass that test point on subsequently tested products. The probe might be missing because of a data processing error, or the fixture assembler may simply forget to install and wire it. Similarly, if a spring probe is shorted to an adjacent spring probe within the fixture, then this connection will appear on all products during test, and any real short circuit of these points on the product will be masked. The same problems of missing or shorted pins apply to pin translator style fixtures for Universal Grid type test systems.

The worst problem lies in the very nature of self–learn as a comparison technique. Any errors common to all products will be totally undetected. Similarly, there is no means of checking the appropriateness of the fixture to the product. Board manufacturers use various CAM tools to process the original board design data for panelization and other tool setups. It is not uncommon that a problem in artwork processing, lamination, plating or drilling, will result in the same error appearing on all boards in a given lot. In this case, the self–learn program created from one board may well match most (or even all) of the rest. Electrical test will fail to identify the defect simply because it is a consistent fault. Disaster results, if an entire lot of boards is loaded with valuable components before the defect is found. If repair is difficult or impossible, the significant delay and financial loss occur.

In spite of these defects, the self–learn method remains in use, even in those cases where specifiers have provided Gerber or CAD data. There are a variety of reasons. A vendor may not have effective Gerber or CAD data processing software.Peculiarities in a specific Gerber or CAD product data file may crash available software, and the production schedule is such that correcting the data or software is difficult. A slow Gerber processing station may be severly backlogged with other jobs. Errors during fixture fabrication result in a fixture in which probes are properly located, but are improperly mapped to the test system testpoints. This can occur as a result of as little as a couple of crossed wires or mis-loaded translator pins. Thus, a fixture is completed, the product is ready for test, but a working Gerber or CAD data derived test program is unavailable. Or perhaps the program for an existing Gerber or CAD derived fixture can no longer be located. As the pressure to ship product mounts, self-learn becomes an attractive alternative. There are many reasons why a self-learn program might become attractive. But there is great potential for test 'escapes' with this programming technique. If you want a product to be tested with a Gerber or CAD derived program, be sure to confirm this requirement explicity with the vendor. Provide the vendor accurate product data, in a usable format.

Gerber Net List Method
Test engineers have long recognized the shortcomings and test escapes associated with reliance on self–learned programs and manual fixture data creation. Given that circuit boards are now almost universally designed using CAD systems, the solution is certainly to automate test program generation and fixture fabrication data from the same database used to create the board itself.

However the test engineer at a typical PCB manufacturing operation confronts incompatible databases from myriad types of customer–owned CAD systems. While industry organizations have worked toward standardization of high–level data interchange, an intermediate solution has evolved. This is the Gerber method.

Test Engineers noted that each of the CAD systems was already required to output the Gerber photoplot format information used to create the artwork images for each layer of a given board. A number of vendors have created software designed to analyze this image data, and to create new databases from it. In each case, the photoplot files are loaded intoa computer containing processing software. (These files include Gerber photoplots for each layer, the drill file, and a list of aperture shapes used in this particular photoplot.)

The extracted data includes desired probe locations, testpoint numbers assigned to these probes, and a topological netlist. The netlist describes the interconnection of testpoints at specific locations by the conductor patterns of the board. The netlist is then formatted for a given specific test system, stated in terms of the testpoint assigned to each location within the fixture. Output data also includes the drill and wiring files for the fixture (or drill and pin load files for grid type fixtures). Ideally, the result is a test fixture and test program that match each other, and the product.

The Gerber method is widely used at present. It offers considerable improvement over the self–learn approach. When the entire process is well controlled, the result is an effective test of the product to the same data used in its manufacture. When the first boards off the line do not match this expectation, the results are examined.

It is very important that the fixture be assembled and wired (or loaded with pins) precisely as prescribed by the Gerber-derived data. Otherwise, the test fixture will not match the test program. (Testpoint identifications will be mixed up.) Sometimes, rather than laborious debugging of the fixture problems, and correction of either the fixture or test program, time pressure may tempt the operator to simply self–learn a replacement program. If this occurs, any consistent product errors will be completely overlooked, as will other types of fixture problems.

Despite its popularity, the Gerber method exhibits certain shortcomings. The Gerber data is not particularly well suited to this purpose. There are so many ways to photoplot a given feature that the software routines, intended to recognize product features as deserving a testpoint, become subject to error. This problem usually becomes more serious as the board becomes more complex. In addition, the Gerber file contains a lot of data that is of no value to the test process, and working through this information consumes considerable time.

Because the data is complex, automatic placement and optimization of testpoint assignment is usually followed by manual cleanup and editing. This introduces a human error opportunity.

Some older software packages are so clumsy that users are tempted to shortcut the process. They will use the Gerber processing software to generate the test fixture data, but then shortcut generation of a test program by falling back to the test system's self–learn capability. This decision also results in loss of control of the fixture assembly process, since precise testpoint mapping is now insignificant. Of course, any consistent errors in either product or fixture will remain completely undetected.

The most serious drawback of the Gerber process, at least from a theoretical point of view, is that it really is testing the board according to the manufacturing database, rather than the design database. This is because the Gerber information has normally gone through a variety of manipulations on CAM stations before it is processed into fixture and test program databases. Therefore, any errors in the CAM process are incorporated in the test program and fixture, and will remain undetected. This is the critical distinction between the Gerber method. and the CAD Net List method described below.

Cad Net List Method
Engineers and Quality Managers recognize the limitations of the Gerber approach, as well as its advantages over self–learn. Direct extraction of fixture and test program data from the original design specifications is the next step forward. Full implementation of this capability requires a degree of cooperation from the original board designer/ specifier. The CAD system employed should be able to output data in a recognized standard format, or a post processor should be created to perform this task. IPC–D–356 defines one such data interchange standard, and is gaining increased acceptance.

For each testpoint location on the product, a test database should define at least:

• Network Identity
• X–Y Location
• Testpoint Access Side
• End Of Net vs. Midpoint Status
• Type and Dimensions of the Feature

The X–Y and side access information is used to locate testpoints. The network identity will place the testpoint correctly within the test program net list. The midpoint flag indicates that the feature is not the endpoint of a network, and need not be probed. The feature information is used to determine probe tip size and style, as well as for staggering of fine pitch–probes to maximize spacing.

All of this information is known by the original board design CAD system, and in providing the information explicitly, the specifier gains effective control of the test process. The availability of this information in a standardized format (such as IPC–D356) is the primary limitation on the application of this method.

With this method, it remains very important that the fixture be assembled exactly according to the resulting fixture fabrication data. One advantage of this method is the increased likelihood that an error in either the fixture or test program will result in test results pointing to the error. Ideally, the test fixture is subjected to its own electrical test procedure after assembly. This procedure would check for shorts, opens, and improper routing of wires or pins.

The CAD Net List method is the only one which effectively closes the loop from original design to final electrical test. Fault coverage includes board manufacturing errors, CAM processing errors, and fixture fabrication errors. In addition, the data processing time for this data format is significantly less than that required for Gerber processing.

Summary
The process of final electrical test of bare PCBs has become more complex and more important as the complexity of the boards increases. Loading very expensive electronic components on defective circuit boards can be costly and potentially catastrophic. Specifiers who develop a basic understanding of the practical aspects of the real world test environment can significantly improve their control over the quality of the circuit boards they receive from their vendor.

Do not simply assume that your boards will be tested, and do not rely upon a vague assurance of 100% test. Ideally, provide CAD data in a format such as IPC–D–356 to define desired testpoint locations and netlist. Work closely with your vendor, and ensure that any data processing snags are resolved effectively. Failing the ability to provide and/or process CAD data, provide at least the required Gerber information. With the Gerber data, carefully specify your rules for testpoint placement and dual–side access. In any event, consult with the circuit designer and evolve meaningful continuity and isolation test thresholds, without rendering the test process needlessly expensive.

Board manufacturers are eager to assist in this process, and can be an excellent starting point in developing effective test specifications. Be sure your vendor has the equipment needed to meet your electrical measurement and stimulus voltage requirements. Evaluate the ability of the test equipment to accept dual–side access testheads, and evaluate existing data processing equipment for Gerber and/or CAD data. Check for any required special facilities for embedded resistor or characteristic impedance test.

Specific Test Requirement Examples
The following suggestions for compact board test specifications may be useful as guidelines, specific to different end uses of the bare–boards. In some cases, they reflect the limits of what can be done with mainstream state–of–the–art test equipment and fixtures.

For General Digital And Microprocessor Applications:
Boards shall be tested according to the requirements and guidelines of IPC–ET–652 except as noted below:

1.Testpoints shall be assigned to all physical endpoints of networks and network branches. This includes all surface–mount component features and cardedge connector features which terminate networks, plus component mounting holes connected only to internal layers.

2. Testpoints shall be assigned to all singlepoint networks.

3. The test fixture used shall be able to contact all assigned testpoints simultaneously. If testpoints are required on both sides of the board, a test fixture providing simultaneous dualside access to all testpoints shall be employed.

4. Continuities shall be verified with a test threshold not in excess of 10 ohms, as measured at the probe tips of the fixture employed, and using a test current of 50 milliamperes or less. Maximum open-circuit voltage during continuity test shall not exceed 20 volts.

5. Isolation of each network shall be verified with a test threshold of at least 10 Megohms, measured with a voltage of between 95 and 105 volts applied to passing networks. The test system shall incorporate means of limiting the energy delivery to failing (shorted) networks such that tested products are not damaged.

6. The electrical test program and test fixture shall be generated from the supplied Gerber or CAD database files.

7. Any board reworked or repaired in any way following electrical test shall be subjected to a completely repeated electrical test according to the requirements given above. A board shall not be considered to have passed the electrical test until it passes according to the data–derived test program in a single test cycle.

Analog, high–speed digital, RF, or other high–performance applications
The following data might be applied to boards where the value of components added to the board is fairly high, and circuit performance requirements will be affected by subtle board problems. In this case, use the suggestions listed above substituting the following changes:

4. Continuities shall be verified with a test threshold not in excess of 5 ohms, as measured at the probe tips of the fixture employed, and using a test current of 50 milliamperes or less. Maximum opencircuit voltage during continuity test shall not exceed 20 volts.

5. Isolation of each network shall be verified with a test threshold of at least 100 Megohms, measured with a voltage of between 235 and 265 volts applied to passing networks. The test system shall incorporate means of limiting the energy delivery to failing (shorted) networks such that tested products are not damaged. The isolation test method shall be such that each network is tested individually for the total parallel leakage to all other networks in the product, as a single measurement.

David J. Wilkie is Manager of Systems Engineering, Everett Charles Technologies Test Equipment Division. He has 16 years of electronic and systems design experience. Mr. Wilkie holds a BSEE degree from California Polytechnic University in Pomona, CA. He is a member of IEEE, and is ECT's official representative to IPC.