BEND IT MEND IT

The Hidden Cost of Board Stress in Test

By:

Steve Green,
Everett Charles Technologies

I doubt that in today's market that there is a single OEM or CEM that would guarantee their loaded printed circuit boards (typically 1.6mm thick) to undergo a 1,500 lbs stress test. And yet a 3,000 point test fixture utilizing 8oz. POGO® test probes is doing just that.

3,000 point test fixtures with 8oz. of force are not uncommon today. Just look at the test point capacity of the major ATE vendors; Genrad, HP, & Teradyne. Currently Genrad testers top the scales with an 8,000 point test system, HP at 5,500, and Teradyne at 4,500. An interesting visual here, is to imagine the tester sitting on top of the UUT. The average ICT tester weighs in at less than 1,500 Lbs. Thankfully it's not practical to raise and lower the tester onto the boards, if it were, we'd all be a little more concerned about 'BOARD STRESS'.

Fortunately for some industries reducing their product size is not an issue, but to others, it's a matter of life and death. The net result is what most test engineers have to live with: high test point counts, no-clean, smaller test pad geometries, reduced surface area, and higher test point density. Look at the effect of PCB size reduction in the following example:

A PCB 12x12 inches square, with 3000 8oz. POGO®s equates to 10.42 lbs. of force per square inch. Keeping the probe count the same reduce the board size down to 9x9 inches and you have 18.52 lbs. per square inch, and then down to 6x6 inches and we have 41.67 lbs. of force per square inch. This problem is made worse by the fact that no PCB has a linear test footprint, Just do a test point measles chart to see this. Add to this a No-Clean environment demanding higher spring force probes to cut through contaminants.

The net effect is higher density probing and the potential for board stress.

Having now some appreciation of the total force distributed across the surface of a PCB under test, let's take a look at how fixture builders address the uneven stress forces displaced across the surface of the UUT. The forces acting on the UUT are predominantly shared between the top and bottom side, nullifying one another if contact points are mirrored exactly by a support stops of some description. Unfortunately it is almost impossible to do this. The ability to nullify the forces using support gaskets and hold down gate 'push fingers' is limited by the design of the PCB itself.

The forces acting on the UUT are distributed to both sides. This occurs as follows:

1. UUT bottom side POGO® test probes.
2. Push fingers in a hold down gate assembly.
3. UUT Top side POGO® test probes.
4. Support gaskets and delrin stops.
5. Vacuum sealed boards have Atmospheric pressure top side and bottom side POGO® test probe contact points.

Boards that are vacuum sealed are placed on a molded gasket, here atmospheric pressure pushes the UUT down at 14.7 lbs. per square inch (perfect vacuum seal). This in the case of our example PCB measuring 12 x 12 inches equates to 2116.8 lbs. of force distributed across the entire surface of the UUT. The underside support gasket needs to contact as much of the UUT's underside surface as possible in order to minimize flexing.

Fig 1. Standard Vacuum sealed fixture.

The above gasketing technique can be enhanced to provide even more support by a technique referred to as 'Zero Flex'™. This is where the Fixture's top plate is routed to the exact profile of the underside of the UUT with its components. The gasket has a recessed perimeter seal which is laid in the routed profile of the well. Now the underside profile of the UUT is fully supported by the G10 top-plate.

Going forward the need to control board flex will grow, and the answer to many a test and production engineers prayers would be to quantify and visualize the board flex that will occur prior to manufacture. This we are now seeing, certain OEMs are now requiring FEA (Finite Element Analysis) prior to completing the PCB component layout. Thus allowing stress visualization before the UUT is committed to production layout. The benefits are huge.

The Board Stress Analysis process starts with the test point X,Y data and POGO® spring forces. The next stage is to enter the support positions, such as gaskets or hold down gate push fingers.

Following this a mesh grid is applied to the geometry of the UUT, as seen here in fig 4.

Then Board Stress Analysis can be run, producing a visual color coded stress map of the surface of the board:

As we move to higher node count boards with less free space on the UUT for test pad distribution we will see areas of high density probing occur, Just take a look at the some of the BGA packages today with 400-500 test points on a device less than 2 inches square. These high density probing points can cause uncontrollable board flex. Where this occurs the potential to damage stress sensitive components such as multilayer ceramic capacitors (MLCs) is high. The worst scenario is to have the boards pass but suffer stress related damage which results in infant mortality.

One of the interesting things to note is that this technology has been about for over a decade, and yet it is only of late that CEMs and OEMs are starting to use this tool to review the potential ATE fixture induced board stress, at the CAD PCB layout stage of the board design. The ability to predict and visualize the stressing that will occur is now a vital task. Some test engineers are now requiring this service and feeding the results back to the CAD department, with requests to relocate components to produce a more even test point layout. This interaction between test and design will become less as more design engineers become familiar with fixture induced board stress.

The BSA process needs to become a standard routine at design. This will even out high density areas of concern, and present production test with an optimized design.